Microelectronic complexes, specifically systems and groups of discrete microelectronic functional modules, implement an important range of electronic devices, including microcomputers and microprocessors, and have important application in the design of electronic systems. Examples of such microelectronic complexes include Printed Circuit Boards (PCBs) containing a plurality of chips and/or integrated circuits, as well as Large-Area Integrated Circuits (LAICs), such as semi-conductor wafers, containing a plurality of microelectronic components. Essential to these microelectronic complexes are the data buses, which interconnect the discrete functional modules and allow the transfer of data from one connected module to any other.
In the case of a LAIC implemented on a semi-conductor wafer, the LAIC is typically divided into a plurality of discrete functional cells, each cell including at least one integrated circuit. These cells are laid out within a dedicated area on the wafer surface, and may form a grid-like array. Each cell has thousands, if not tens of thousands, of connections to other cells. The cells are formed on the wafer using patterned reticles, where, for each lithographic layer, a single reticle may be used repeatedly to form a common cell having multiple occurrences on the wafer.
Data buses are used to interconnect the various cells of the wafer, and are typically formed of one or more wire bundles, each bundle including a set of data and control wires. The wire bundles of a data bus are formed on the wafer body such that they are proximate and run parallel to the longitudinal axis of a row of cells. Reticles are also designed and used for forming the buses on the semiconductor material of the wafer.
In the case of a PCB, the PCB is similarly divided into a plurality of cells, where each cell is a discrete chip. In contrast with a LAIC, a PCB does not necessarily contain a plurality of identical sub-regions. However, data buses are used on PCBs, as on LAICs, to interconnect the various chips of the PCB.
Typically, the buses used on PCBs or LAICs have their wire bundles laid out in parallel. The highest performance interconnect for a row of cells is to have each cell in the row of cells transmit to a different wire bundle of the bus and to receive from every wire bundle of the bus. Each cell is connected to the different wire bundles of the bus by means of a set of connection lines, where the connection lines for a particular cell typically run perpendicular to the wire bundles of the bus.
A common problem associated with the existing high-performance interconnect arrangements used on PCBs and LAICs is that cells may experience difficulty in receiving data from a bus, or data transmitted from a bus to a cell may be lost, due to the increasing number of wire bundles per bus. More specifically, although each cell is connected to receive from every wire bundle of the bus, a typical cell can only receive data from one wire bundle at a time. Unfortunately, the greater the number of wire bundles from which a cell can receive data, the greater the odds that data may be sent simultaneously from different wire bundles to the cell.
Also, in order for each cell to transmit to a different wire bundle of the bus, each cell would normally require a different pattern of connection lines for connecting the transmitter and receivers of the cell to the different wire bundles of the bus. Accordingly, no two cells use the same pattern of connection lines, and a different reticle is required for each cell in order to form the different connection patterns. Obviously, both the cost and fabrication time associated with the wafer manufacturing process would increase with the number of different reticles required, while the efficiency of the process would decrease.
Existing solutions to render the wafer manufacturing process more efficient include the provision of a high-performance braided bus with interweaved wire bundles, where the bundles form a periodically repeating pattern. Within each period of the repeating pattern, the wire bundles of the bus are arranged according to a certain order, where this order changes from one period to the next such that each position within the order is occupied by a different wire bundle in each period. The repeating pattern allows the cells to share a common arrangement of connection lines for connecting to different conductive paths of the data bus, which reduces the number of different reticles required to manufacture the interconnect arrangement.
Unfortunately, the braided bus displays certain weaknesses, notably timing discrepancies in the signal transmission. From one period of the repeating pattern to the next, each wire bundle jumps from one position in the order to another position. However, while one wire bundle may jump one position, another may jump four positions. Accordingly, the different wire bundles of the bus define different path lengths between adjacent cells, such that timing differences arise for data transmission over different wire bundles. Further, even if a high-performance interconnect arrangement on a PCB or LAIC uses the braided bus, this does not solve the above-described difficulty experienced by cells in receiving data from several different wire bundles of a bus simultaneously. Against this background, it clearly appears that a need exists in the industry for an improved high-performance interconnect arrangement for an array of discrete functional modules.